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master's thesis
Arbitražni multiplekser
2022. urn:nbn:hr:179:595610
Turalija, Marin
University of Split
Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture
Department of Electronics and Computing

Cite this document

Turalija, M. (2022). Arbitražni multiplekser (Master's thesis). Split: University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture. Retrieved from https://urn.nsk.hr/urn:nbn:hr:179:595610

Turalija, Marin. "Arbitražni multiplekser." Master's thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, 2022. https://urn.nsk.hr/urn:nbn:hr:179:595610

Turalija, Marin. "Arbitražni multiplekser." Master's thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, 2022. https://urn.nsk.hr/urn:nbn:hr:179:595610

Turalija, M. (2022). 'Arbitražni multiplekser', Master's thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, accessed 03 January 2025, https://urn.nsk.hr/urn:nbn:hr:179:595610

Turalija M. Arbitražni multiplekser [Master's thesis]. Split: University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture; 2022 [cited 2025 January 03] Available at: https://urn.nsk.hr/urn:nbn:hr:179:595610

M. Turalija, "Arbitražni multiplekser", Master's thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, Split, 2022. Available at: https://urn.nsk.hr/urn:nbn:hr:179:595610

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Metadata
TitleArbitražni multiplekser
Title (english)Arbitration multiplexer
AuthorMarin Turalija
MentorDuje Čoko (mentor)
GranterUniversity of Split
Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture
(Department of Electronics and Computing)
Split
Defense date and country2022-07-14, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Electronics
Abstract
U radu je predstavljen koncept arbitraže i pregled svih tehnoloških rješenja koje nude arbitražu u računalnim sustavima. Predstavljene su dvije podjele arbitraže, centralizirana i distribuirana i obrađene su njihove tehnike. Iza toga slijedi pregled protokola koji se koriste prilikom arbitraže i strukture višeulaznih arbitera. Kako jednostavni arbiteri bez prioriteta nisu dovoljni za današnje moderne primjene predstavljeni su i prioritetni arbiteri s naglaskom na statičke i dinamičke prioritetne arbitere. Kao zadnji dio rada realiziran je sklop koji se sastoji od arbiterskog stabla, enkodera i multipleksera. Sklop je realiziran tako da prikaže način arbitraže i rezerviranja resursa za jednog klijenta gdje je najveći naglasak na arbiterskom stablu. Na kraju je predstavljena softverska implementacija kroz Verilog programski jezik i rezultati testiranja sklopa.
Abstract (english)
This work presents the concept of arbitration and an overview of all technological solutions that offer arbitration in computer systems. Two main divisions of arbitration, centralized and distributed, are presented and their techniques are discussed. This is followed by an overview of the protocols used in arbitration and the structure of multi-input arbitrators. Since simple arbiters without priority are not sufficient for today's modern applications, priority arbiters with an emphasis on static and dynamic priority arbiters are also presented. As the last part of the work, a circuit consisting of an arbitration tree, a priority encoder and a multiplexer was realized. The circuit was realized in such a way as to show the method of arbitration and resource allocation for one client, where the greatest emphasis is on the arbitration tree. At the very end, the software implementation using the Verilog programming language and the circuit testing results are presented.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:179:595610
Study programmeTitle: Electronics and Computer Engineering
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektronike i računalnog inženjerstva (magistar/magistra inženjer/inženjerka elektronike i računalnog inženjerstva)
Type of resourceText
File originBorn digital
Access conditionsAccess restricted to authenticated users
Terms of useLicence In copyright icon
Created on2023-10-02 10:46:52